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| a FEATURES Monolithic 12-Bit 10 MSPS A/D Converter Low Noise: 0.26 LSB RMS Referred-to-Input No Missing Codes Guaranteed Differential Nonlinearity Error: 0.5 LSB Signal-to-Noise and Distortion Ratio: 68 dB Spurious-Free Dynamic Range: 75 dB Power Dissipation: 1.03 W Complete: On-Chip Track-and-Hold Amplifier and Voltage Reference Twos Complement Binary Output Data Out-of-Range Indicator 28-Lead Ceramic DIP or 44-Terminal Leadless Chip Carrier Package VINA VINB T/H Complete 12-Bit 10 MSPS Monolithic A/D Converter AD872A FUNCTIONAL BLOCK DIAGRAM AVDD AGND AVSS DVDD DGND *DRVDD *DRGND AD872A + A/D CLOCK 4 DAC T/H A/D 4 CORRECTION LOGIC REF IN REF OUT REF GND OTR MSB *MSB BIT2-BIT12 *OEN *ONLY AVAILABLE ON 44-TERMINAL SURFACE MOUNT PACKAGE +2.5V REFERENCE OUTPUT BUFFERS DAC + T/H A/D 3 DAC 4 + A/D PRODUCT DESCRIPTION The AD872A is a monolithic 12-bit, 10 MSPS analog-to-digital converter with an on-chip, high performance track-and-hold amplifier and voltage reference. The AD872A uses a multistage differential pipelined architecture with error correction logic to provide 12-bit accuracy at 10 MSPS data rates and guarantees no missing codes over the full operating temperature range. The AD872A is a redesigned version of the AD872 which has been optimized for lower noise. The AD872A is pin compatible with the AD872, allowing the parts to be used interchangeably as system requirements change. The low noise input track-and-hold (T/H) of the AD872A is ideally suited for high-end imaging applications. In addition, the T/H's high input impedance and fast settling characteristics allow the AD872A to easily interface with multiplexed systems that switch multiple signals through a single A/D converter. The dynamic performance of the T/H also renders the AD872A suitable for sampling single channel inputs at frequencies up to and beyond the Nyquist rate. The AD872A provides both reference output and reference input pins, allowing the onboard reference to serve as a system reference. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. A single clock input is used to control all internal conversion cycles. The digital output data is presented in twos complement binary output format. An out-ofrange signal indicates an overflow condition, and can be used with the most significant bit to determine low or high overflow. The AD872A is fabricated on Analog Devices' ABCMOS-l process that utilizes high speed bipolar and CMOS transistors on a single chip. The AD872A is packaged in a 28-lead ceramic DIP and a 44terminal leadless ceramic surface mount package (LCC). Operation is specified from 0C to +70C and -55C to +125C. PRODUCT HIGHLIGHTS The AD872A offers a complete single-chip sampling, 12-bit 10 MSPS analog-to-digital conversion function in a 28-lead DIP or 44-terminal LCC. Low Noise--The AD872A features 0.26 LSB rms referred toinput noise. Low Power--The AD872A at 1.03 W consumes a fraction of the power of presently available hybrids. On-Chip Track-and-Hold (T/H)--The low noise, high impedance T/H input eliminates the need for external buffers and can be configured for single-ended or differential inputs. Ease of Use--The AD872A is complete with T/H and voltage reference and is pin-compatible with the AD872. Out of Range (OTR)--The OTR output bit indicates when the input signal is beyond the AD872A's input range. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1997 AD872A-SPECIFICATIONS DC SPECIFICATIONS (T Parameter RESOLUTION MAX CONVERSION RATE INPUT REFERRED NOISE ACCURACY Integral Nonlinearity (INL) Differential Nonlinearity (DNL) No Missing Codes Zero Error (@ +25C)2 Gain Error (@ +25C)2 TEMPERATURE DRIFT Zero Error Gain Error3, 4 Gain Error3, 5 POWER SUPPLY REJECTION6 AVDD , DVDD (+5 V 0.25 V) AVSS (-5 V 0.25 V) ANALOG INPUT Input Range Input Resistance Input Capacitance INTERNAL VOLTAGE REFERENCE Output Voltage Output Voltage Tolerance Output Current (Available for External Loads) (External Load Should Not Change During Conversion) REFERENCE INPUT RESISTANCE POWER SUPPLIES Supply Voltages AVDD AVSS DVDD DRVDD 7 Supply Current IAVDD IAVSS IDVDD IDRVDD7 POWER CONSUMPTION MIN to TMAX, AVDD = + 5 V, DV DD = +5 V, AVSS = -5 V, f SAMPLE = 10 MHz unless otherwise noted) J Grade1 12 10 0.26 1.75 0.5 12 0.75 1.25 0.15 0.80 0.25 0.125 0.125 1.0 50 10 2.5 20 2.0 5 S Grade1 12 10 0.26 1.75 0.5 12 0.75 1.25 0.3 1.75 0.50 0.125 0.125 1.0 50 10 2.5 40 2.0 5 Units Bits min MHz min LSB rms typ LSB typ LSB typ Bits Guaranteed % FSR max % FSR max % FSR max % FSR max % FSR max % FSR max % FSR max V max k typ pF typ V typ mV max mA typ k +5 -5 +5 +5 91 147 20 2 1.03 1.25 +5 -5 +5 +5 92 150 21 2 1.03 1.3 V ( 5% AVDD Operating) V ( 5% AVSS Operating) V ( 5% DVDD Operating) V ( 5% DRVDD Operating) mA max (85 mA typ) mA max (115 mA typ) mA max (7 mA typ) mA W typ W max NOTES 1 Temperature ranges are as follows: J Grade: 0C to +70C, S Grade: -55C to +125C. 2 Adjustable to zero with external potentiometers (see Zero and Gain Error Calibration section). 3 +25C to T MIN and +25C to T MAX. 4 Includes internal voltage reference drift. 5 Excludes internal voltage reference drift. 6 Change in Gain Error as a function of the dc supply voltage (V NOMINAL to VMIN, VNOMINAL to VMAX ). 7 LCC package only. Specifications subject to change without notice. -2- REV. A AD872A AC SPECIFICATIONS (T Parameter SIGNAL-TO-NOISE & DISTORTION RATIO (S/N+D) fINPUT = l MHz fINPUT = 4.99 MHz SIGNAL-TO-NOISE RATIO (SNR) fINPUT = 1 MHz fINPUT = 4.99 MHz TOTAL HARMONIC DISTORTION (THD) fINPUT = 1 MHz fINPUT = 4.99 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fINPUT = l MHz fINPUT = 4.99 MHz INTERMODULATION DISTORTION (IMD)2 Second Order Products Third Order Products FULL POWER BANDWIDTH SMALL SIGNAL BANDWIDTH APERTURE DELAY APERTURE JITTER ACQUISITION TO FULL-SCALE STEP OVERVOLTAGE RECOVERY TIME MIN to TMAX, AVDD = + 5 V, DV DD = +5 V, AVSS = -5 V, f SAMPLE = 10 MHz unless otherwise noted) 1 J Grade 68 61 66 69 67 -74 -63 -72 75 74 -80 -73 35 35 6 16 40 40 S Grade 68 61 66 69 67 -74 -62 -72 75 74 -80 -73 35 35 6 16 40 40 Units dB typ dB min dB typ dB typ dB typ dB typ dB max dB typ dB typ dB typ dB typ dB typ MHz typ MHz typ ns typ ps rms typ ns typ ns typ NOTES 1 f INPUT amplitude = -0.5 dB full scale unless otherwise indicated. All measurements referred to a 0 dB (1.0 V pk) input signal unless otherwise indicated. 2 fa = 1.0 MHz, fb = 0.95 MHz with t SAMPLE = 10 MHz. Specifications subject to change without notice. DIGITAL SPECIFICATIONS (T Parameter MIN to TMAX, AVDD = + 5 V, DV DD = +5 V, AVSS = -5 V, f SAMPLE = 10 MHz unless otherwise noted) Symbol VIH VIL IIH IIL CIN VOH VOL COUT IZ J, S Grades +2.0 +0.8 115 115 5 +2.4 +0.4 5 10 Units V min V max A max A max pF typ V min V max pF typ A max LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current (VIN = DVDD) Low Level Input Current (VIN = 0 V) Input Capacitance LOGIC OUTPUT High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 1.6 mA) Output Capacitance Leakage (Three State, LCC Only) Specifications subject to change without notice. REV. A -3- AD872A SWITCHING SPECIFICATIONS V Parameter Clock Period CLOCK Pulsewidth High CLOCK Pulsewidth Low Clock Duty Cycle2 Output Delay Pipeline Delay (Latency) Data Access Time (LCC Package Only)2 Output Float Delay (LCC Package Only)2 1 (TMIN to TMAX with AV DD = +5 V, DVDD = +5 V, DRVDD = +5 V, AVSS = -5 V; VIL = 0.8 V, IN = 2.0 V, V OL = 0.4 V and VOH = 2.4 V) Symbol tC tCH tCL tOD tDD tHL J, S Grades 100 45 45 40 60 10 3 50 50 Units ns min ns min ns min % min (50% typ) % max ns min (20 ns typ) Clock Cycles ns typ (100 pF Load) ns typ (10 pF Load) NOTES 1 Conversion rate is operational down to 10 kHz without degradation in specified performance. 2 See section on Three-State Outputs for timing diagrams and applications information. Specifications subject to change without notice. N VIN N+1 tC CLOCK N N+1 tCH BIT 2-12 MSB, OTR tCL DATA N tOD DATA N+1 Figure 1. Timing Diagram ABSOLUTE MAXIMUM RATINGS 1 Parameter AVDD AVSS DVDD, DRVDD2 DRVDD 2 DRGND AGND AVDD Clock Input, OEN2 Digital Outputs VINA, VINB, REF IN REF IN Junction Temperature Storage Temperature Lead Temperature (10 sec) With Respect to AGND AGND DGND, DRGND2 DVDD DGND DGND DVDD DGND DGND AGND AGND Min -0.5 -6.5 -0.5 -6.5 -0.3 -1.0 -6.5 -0.5 -0.5 -6.5 AV SS -65 Max +6.5 +0.5 +6.5 +6.5 +0.3 +1.0 +6.5 DVDD + 0.5 DVDD + 0.3 +6.5 AV DD +150 +150 +300 Units Volts Volts Volts Volts Volts Volts Volts Volts Volts Volts Volts C C C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. 2 LCC package only. -4- REV. A AD872A PIN DESCRIPTION Symbol VINA VINB AVSS AVDD AGND DGND DVDD BIT 12 (LSB) BIT 2-BIT 11 MSB OTR CLK REF OUT REF GND REF IN DRVDD NC DRGND OEN BIT 1 DIP LCC Pin No. Pin No. 1 2 3, 25 4 5, 24 6, 23 7, 22 8 18-9 19 20 21 26 27 28 N/A N/A N/A N/A N/A 1 2 5, 40 6, 38 9, 36 10 33 16 26-17 29 30 31 41 42 43 12, 32 3, 4, 7, 8, 14, 15, 28, 35, 37, 39, 44 11, 34 13 27 Type AI AI P P P P P DO DO DO DO DI AO AI AI P Name and Function (+) Analog Input Signal on the differential input amplifier. (-) Analog Input Signal on the differential input amplifier. -5 V Analog Supply. +5 V Analog Supply. Analog Ground. Digital Ground. +5 V Digital Supply. Least Significant Bit. Data Bits 2 through 11. Inverted Most Significant Bit. Provides twos complement output data format. Out of Range is Active HIGH on the leading edge of Code 0 or the trailing edge of Code 4096. See Output Data Format Table III. Clock Input. The AD872A will initiate a conversion on the rising edge of the clock input. See the Timing Diagram for details. +2.5 V Reference Output. Tie to REF IN for normal operation. Reference Ground. Reference Input. +2.5 V input gives 1 V full-scale range. +5 V Digital Supply for the output drivers. No Connect. P DI DO Digital Ground for the output drivers. (See section on Power Supply Decoupling for details on DRVDD and DRGND.) Output Enable. See the Three State Output Timing Diagram for details. Most Significant Bit. TYPE: AI = Analog Input; AO = Analog Output; DI = Digital Input; DO = Digital Output; P = Power; N/A = Not Available on 28-lead DIP. Only available on 44-terminal surface mount package. PIN CONFIGURATIONS 28-Lead Ceramic DIP AVDD 44-Terminal LCC REF GND REF IN REF OUT 41 AVSS VINB VINA NC VINA 1 VINB 2 AVSS AVDD 3 4 28 REF IN 27 REF GND 26 REF OUT 25 AVSS NC 7 NC 8 AGND 9 6 5 NC 4 3 2 1 44 NC 43 42 40 39 38 37 36 AVSS NC AVDD NC AGND NC DRGND DVDD DRVDD CLK OTR MSB 35 34 33 32 31 30 29 28 AGND 5 DGND 6 AD872A 24 AGND 23 DGND TOP VIEW DVDD 7 (Not to Scale) 22 DVDD 21 CLK 20 OTR 19 MSB 18 BIT 2 17 BIT 3 16 BIT 4 15 BIT 5 DGND 10 DRGND 11 DRVDD 12 OEN 13 NC 14 NC 15 BIT 12 (LSB) 16 BIT 11 17 18 19 20 21 22 23 24 25 26 27 AD872A TOP VIEW (NOT TO SCALE) BIT 12 (LSB) 8 BIT 11 9 BIT 10 10 BIT 9 11 BIT 8 12 BIT 7 13 BIT 6 14 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 2 BIT 1 (MSB) BIT 5 NC = NO CONNECT REV. A -5- BIT 4 BIT 3 NC AD872A DEFINITIONS OF SPECIFICATIONS LINEARITY ERROR (INL) OVERVOLTAGE RECOVERY TIME Linearity error refers to the deviation of each individual code from a line drawn from "negative full scale" through "positive full scale." The point used as "negative full scale" occurs 1/2 LSB before the first code transition. "Positive full scale" is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. DIFFERENTIAL LINEARITY ERROR (DNL, NO MISSING CODES) Overvoltage recovery time is defined as that amount of time required for the ADC to achieve a specified accuracy after an overvoltage (50% greater than full-scale range), measured from the time the overvoltage signal reenters the converter's range. DYNAMIC SPECIFICATIONS SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. TOTAL HARMONIC DISTORTION (THD) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 12-bit resolution indicates that all 4096 codes must be present over all operating ranges. ZERO ERROR THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. INTERMODULATION DISTORTION (IMD) The major carry transition should occur for an analog value 1/2 LSB below analog common. Zero error is defined as the deviation of the actual transition from that point. The zero error and temperature drift specify the initial deviation and maximum change in the zero error over temperature. GAIN ERROR The first code transition should occur for an analog value 1/2 LSB above nominal negative full scale. The last transition should occur for an analog value 1 1/2 LSB below the nominal positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. TEMPERATURE DRIFT With inputs consisting of sine waves at two frequencies, fa and fb, any device with nonlinearities will create distortion products, of order (m + n), at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3 . . . . Intermodulation terms are those for which m or n is not equal to zero. For example, the second order terms are (fa + fb) and (fa - fb), and the third order terms are (2 fa + fb), (2 fa - fb), (fa + 2 fb) and (2 fb - fa). The IMD products are expressed as the decibel ratio of the rms sum of the measured input signals to the rms sum of the distortion terms. The two signals are of equal amplitude and the peak value of their sums is -0.5 dB from full scale. The IMD products are normalized to a 0 dB input signal. FULL-POWER BANDWIDTH The temperature drift for zero error and gain error specifies the maximum change from the initial (+25C) value to the value at TMIN or TMAX. POWER SUPPLY REJECTION The full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3 dB for a full-scale input. SPURIOUS FREE DYNAMIC RANGE The specifications show the maximum change in the converter's full scale as the supplies are varied from nominal to min/max values. APERTURE JITTER The difference, in dB, between the rms amplitude of the input signal and the peak spurious signal. ORDERING GUIDE Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the A/D. APERTURE DELAY Model AD872AJD AD872AJE AD872ASD2 AD872ASE2 Temperature Range 0C to +70C 0C to +70C -55C to +125C -55C to +125C Package Option1 D-28 E-44A D-28 E-44A Aperture delay is a measure of the Track-and-Hold Amplifier (THA) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion. NOTES 1 D = Ceramic DIP, E = Leadless Ceramic Chip Carrier. 2 MIL-STD-883 version will be available; contact factory. -6- REV. A Dynamic Characteristics-Sample Rate: 10 MSPS-AD872A 70 68 66 AMPLITUDE - dB 64 S/(N+D) - dB 62 60 58 56 54 52 50 105 106 INPUT FREQUENCY - Hz 107 -95 105 106 INPUT FREQUENCY - Hz 107 -90 3RD HARMONIC -6.0 dB -0.5 dB -75 2ND HARMONIC -70 THD -80 -85 Figure 2. AD872A S/(N+D) Input Frequency Figure 3. AD872A Distortion vs. Input Frequency, Full-Scale Input 1 HARMONICS - dB 2ND -73 3RD -82 4TH -87 5TH -90 6TH -92 7TH -95 8TH -95 9TH -93 f IN = 1MHz f IN AMPLITUDE = -0.5dB THD = 73dB S/(N+D) = 68dB SNR = 70dB SFDR = 73dB 15dB/ DIV 2 3 4 9 8 7 6 5 Figure 4. AD872A Typical FFT, fIN = 1 MHz, fIN Amplitude = -0.5 dB 1 f IN = 1MHz f IN AMPLITUDE = -6.0dB THD = -77dB S/(N+D) = 65dB SNR = 65dB SFDR = 81dB HARMONICS - dB 2ND -81 3RD -97 4TH -91 5TH -84 6TH -88 7TH -90 8TH -90 9TH -94 15dB/ DIV 2 9 8 3 7 4 6 5 Figure 5. AD872A Typical FFT, fIN = 1 MHz, fIN Amplitude = -6 dB REV. A -7- AD872A-Dynamic Characteristics-Sample Rate: 10 MSPS 1 HARMONICS - dB 2ND -75 3RD -88 4TH -93 5TH -87 6TH -86 7TH -90 8TH -91 9TH -94 f IN = 750kHz f IN AMPLITUDE = -0.5dB THD = -74dB S/(N+D) = 69dB SNR = 71dB SFDR = 75dB 15dB/ DIV 2 3 4 9 5 6 8 7 Figure 6. AD872A Typical FFT, fIN = 750 kHz 1 HARMONICS - dB 2ND -75 3RD -93 4TH -85 5TH -85 6TH -89 7TH -97 8TH -90 9TH -92 f IN = 5MHz f IN AMPLITUDE = -0.5dB THD = -74dB S/(N+D) = 65dB SNR = 65dB SFDR = 69dB 15dB/ DIV 2 4 5 9 Figure 7. AD872A Typical FFT, fIN = 5 MHz 700000 618061 600000 NUMBER OF CODE HITS 80 100 x p( CODE X + 1) 500000 400000 300000 200000 100000 19559 0 -1 0 15170 +1 10 0 CODE X CODE X + 1 70 60 50 0.26 LSB RMS 40 30 20 100 90 DEVIATION FROM CORRECT CODE - LSB Figure 8. AD872A Output Code Histogram for DC Input Figure 9. AD872A Code Probability at a Transition -8- REV. A AD872A THEORY OF OPERATION The AD872A is implemented using a 4-stage pipelined multiple flash architecture. A differential input track-and-hold amplifier (THA) acquires the input and converts the input voltage into a differential current. A 4-bit approximation of the input is made by the first flash converter, and an accurate analog representation of this 4-bit guess is generated by a digital-to-analog converter. This approximation is subtracted from the THA output to produce a remainder, or residue. This residue is then sampled and held by the second THA, and a 4-bit approximation is generated and subtracted by the second stage. Once the second THA goes into hold, the first stage goes back into track to acquire a new input signal. The third stage provides a 3-bit approximation/subtraction operation, and produces the final residue, which is passed to a final 4-bit flash converter. The 15 output bits from the 4 flash converters are accumulated in the correction logic block, which adds the bits together using the appropriate correction algorithm, to produce the 12-bit output word. The digital output, together with overrange indicator, is latched into an output buffer to drive the output pins. The additional THA inserted in each stage of the AD872A architecture allows pipelining of the conversion. In essence, the converter is converting multiple inputs simultaneously, processing them through the converter chain serially. This means that while the converter is capable of capturing a new input sample every clock cycle, it actually takes three clock cycles for the conversion to be fully processed and appear at the output. This "pipeline delay" is often referred to as latency, and is not a concern in most applications, however there are some cases where it may be a consideration. For example, some applications call for the A/D converter to be placed in a high speed feedback loop, where its input is servoed to provide a desired result at the digital output (e.g., offset calibration or zero restoration in video applications). In these cases the three clock cycle delay through the pipeline must be accounted for in the loop stability calculations. Also, because the converter is working on three conversions simultaneously, major disruptions to the part (such as a large glitch on the supplies or reference) may corrupt three data samples. Finally, there will be a minimum clock rate below which the THA droop corrupts the signal in the pipeline. In the case of the AD872A, this minimum clock rate is 10 kHz. The high impedance differential inputs of the AD872A allow a variety of input configurations (see APPLYING THE AD872A), The AD872A converts the voltage difference between the VINA and VINB pins. For single-ended applications, one input pin (VINA or VINB) may be grounded, but even in this case the differential input can provide a performance boost: for example, for an input coming from a coaxial cable, VINB can be tied to the shield ground, allowing the AD872A to reject shield noise as common mode. The high input impedance of the device minimizes external driving requirements and allows the user to externally select the appropriate termination impedance for the application. The AD872A clock circuitry uses both edges of the clock in its internal timing circuitry (see spec page for exact timing requirements). The AD872A samples the analog input on the rising edge of the clock input. During the clock low time (between the falling edge and rising edge of the clock) the input THA is in track mode; during the clock high time it is in hold. System disturbances just prior to the rising edge of the clock may cause the part to acquire the wrong value, and should be minimized. REV. A While the part uses both clock edges for its timing, jitter is only a significant issue for the rising edge of the clock (see CLOCK INPUT section). APPLYING THE AD872A ANALOG INPUTS The AD872A features a high impedance differential input that can readily operate on either single-ended or differential input signals. Table I summarizes the nominal input voltage span for both single-ended and differential modes, assuming a 2.5 V reference input. Table I. Input Voltage Span VINA Single-Ended Differential +1 V -1 V +0.5 V -0.5 V VINB GND GND -0.5 V +0.5 V VINA-VINB +1 V (Positive Full Scale) -1 V (Negative Full Scale) +1 V (Positive Full Scale) -1 V (Negative Full Scale) Figure 10 shows an approximate model for the analog input circuit. As this model indicates, when the input exceeds 1.6 V (with respect to AGND), the input device may saturate, causing the input impedance to drop substantially and significantly reducing the performance of the part. Input compliance in the negative direction is somewhat larger, showing virtually no degradation in performance for inputs as low as -1.9 V. +5V 1.75mA +1.6V VINA OR VINB 1V 5pF AD872A -1.9V 1.75mA -5V Figure 10. AD872A Equivalent Analog Input Circuit Figure 11 illustrates the effect of varying the common-mode voltage of a -0.5 dB input signal on total harmonic distortion. 0 -10 -20 -30 THD - dB -40 -50 -60 -70 -80 -90 -100 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 CM INPUT VOLTAGE - V Figure 11. AD872A Total Harmonic Distortion vs. CM Input Voltage, fIN = 1 MHz, FS = 10 MSPS -9- AD872A Figure 12 shows the common-mode rejection performance vs. frequency for a 1 V p-p common-mode input. This excellent common-mode rejection over a wide bandwidth affords the user the opportunity to eliminate many potential sources of input noise as common mode by using the differential input structure of the AD872A. -20 -30 -40 -50 -60 -70 -80 -90 10 -100 105 106 107 108 0 562 562 U1 VINA VIN ( 0.5V) 536 536 AD872A U2 VINB Figure 15. Single-Ended to Differential Connections; U1, U2 = AD811 or AD9617 CMR - dB The use of the differential input signal can help to minimize even-order distortion from the input THA where performance beyond -70 dB is desired. Figure 16 shows the AD872A large signal (-0.5 dB) and small signal (-20 dB) frequency response. INPUT FREQUENCY - Hz Figures 13 and 14 illustrate typical input connections for singleended inputs. FUND AMP - dB Figure 12. Common-Mode Rejection vs. Input Frequency, 1 V p-p Input -10 -20 -30 1V 1 VINA AD872A 2 VINB -40 -50 104 105 106 INPUT FREQUENCY - Hz 107 108 Figure 13. AD872A Single-Ended Input Connection Figure 16. Full Power (-0.5 dB) and Small Signal Response (-20 dB) vs. Input Frequency 1V RT 1 VINA AD872A 2 VINB The AD872A's wide input bandwidth facilitates rapid acquisition of transient input signals: the input THA can typically settle to 12-bit accuracy from a full-scale input step in less than 40 ns. Figure 17 illustrates the typical acquisition of a full-scale input step. 4500 4000 3500 CODE OUT 3000 2500 2000 1500 1000 500 0 0 10 20 30 40 nsec 50 60 70 80 Figure 14. AD872A Single-Ended Input Connection Using a Shielded Cable The cable shield is used as a ground connection for the VINB input, providing the best possible rejection of the cable noise from the input signal. Note also that the high input impedance of the AD872A allows the user to select the termination impedance, be it 50 ohms, or some other value. Furthermore, unlike many flash converters, most AD872A applications will not require an external buffer amplifier. If such an amplifier is required, we suggest either the AD811 or AD9617. Figure 15 illustrates how external amplifiers may be used to convert a single-ended input into a differential signal. The resistor values of 536 and 562 were selected to provide optimum phase matching between U1 and U2. Figure 17. Typical AD872A Settling Time -10- REV. A AD872A The wide input bandwidth and superior dynamic performance of the input THA make the AD872A suitable for undersampling applications where the input frequency exceeds half the sample frequency. The input THA is designed to recover rapidly from input overdrive conditions, returning from a 50% overdrive in less than 40 ns. Because of the THA's exceptionally wide input bandwidth, some users may find the AD872A is sensitive to noise at frequencies from 10 MHz to 50 MHz that other converters are incapable of responding to. This sensitivity can be mitigated by careful use of the differential inputs (see previous paragraphs). Additionally, Figure 18 shows how a small capacitor (10 pF20 pF for 50 terminated inputs) may be placed between VINA and VINB to help reduce high frequency noise in applications where limiting the input bandwidth is acceptable. The AD872A's reference input impedance is equal to 5 k ( 20%), and its effective noise bandwidth is 10 MHz, with a referred-to-input noise gain of 0.8. For example, the internal reference, with an rms noise of 28 V (using an external 1 F capacitor), contributes 24 V (0.05 LSB) of noise to the transfer function of the AD872A. The full-scale peak-to-peak input voltage is a function of the reference voltage, according to the equation: (VINA = VINB ) Full Scale = 0.8 x (VREF - REF GND ) Note that the AD872A's performance was optimized for a 2.5 V reference input: performance may degrade somewhat for other reference voltages. Figure 20 illustrates the S/(N+D) performance vs. reference voltage for a 1 MHz, -0.5 dB input signal. Note also that if the reference is changed during a conversion, all three conversions in the pipeline will be invalidated. 75 1V 1 VINA 10 OR 20pF AD872A 70 2 VINB S/(N+D) - dB 65 Figure 18. Optional High Frequency Noise Reduction 60 The AD872A will contribute its own wideband thermal noise. As a result of the integrated wideband noise (0.26 LSB rms, referred-to-input), applying a dc analog input may produce more than one code at the output. A histogram of the ADC output codes, for a dc input voltage, will be between one and three codes wide, depending on how well the input is centered on a given code and how many samples are taken. Figure 8 shows a typical AD872A code histogram, and Figure 9 illustrates the AD872A's transition noise. REFERENCE INPUT 55 50 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 REFERENCE INPUT VOLTAGE - V Figure 20. S/(N+D) vs. Reference Input Voltage, fIN = 1 MHz, FS = 10 MHz The nominal reference input should be 2.5 V, taken with respect to REFERENCE GROUND (REF GND). Figure 19 illustrates the equivalent model for the reference input: there is no clock or signal-dependent activity associated with the reference input circuitry, therefore, no "kickback" into the reference. AD872A REF IN 1 5k ( 20%) Table II summarizes various 2.5 V references suitable for use with the AD872A, including the onboard bandgap reference (see REFERENCE OUTPUT section). Table II. Suitable 2.5 V References Drift (ppm/ C) REF43B AD680JN Internal 6 (max) 10 (max) 30 (typ) Initial Accuracy % 0.2 0.4 0.4 REF GND 2 AVSS If an external reference is connected to REF IN, REF OUT must be connected to +5 V. This should lower the current in REF GND to less than 350 A and eliminate the need for a 1 F capacitor, although decoupling the reference for noise reduction purposes is recommended. Alternatively, Figure 21 shows how the AD872A may be driven from other references by use of an external resistor. The external resistor forms a resistor divider with the on-chip 5 k resistor to realize 2.5 V at the reference input pin (REF IN). A trim potentiometer is needed to accommodate the tolerance of the AD872A's 5 k resistor. Figure 19. Equivalent Reference Input Circuit However, in order to realize the lowest noise performance of the AD872A, care should be taken to minimize noise at the reference input. REV. A -11- AD872A 2.55 RT +5V REF 2k 2.5V R 3.9k 5k REF IN 2.54 REFERENCE VOLTAGE - Volts AD872A 2.53 2.52 2.51 2.50 2.49 2.48 2.47 2.46 REF GND Figure 21. Optional +5 V Reference Input Circuit REFERENCE GROUND The REF GND pin provides the reference point for both the reference input, and the reference output. When the internal reference is operating, it will draw approximately 500 A of current through the reference ground, so a low impedance path to the external common is desirable. The AD872A can tolerate a fairly large difference between REF GND and AGND, up to +1 V, without any performance degradation. REFERENCE OUTPUT 2.45 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE - C Figure 23. Reference Output Voltage vs. Temperature 2.50 2.48 The AD872A features an onboard, curvature compensated bandgap reference that has been laser trimmed for both absolute value and temperature drift. The output stage of the reference was designed to allow the use of an external capacitor to limit the wideband noise. As Figure 22 illustrates, a 1 F capacitor on the reference output is required for stability of the reference output buffer. Note: If used, an external reference may become unstable with this capacitor in place. REFERENCE VOLTAGE - V 2.46 2.44 2.42 2.40 1k 10k 100k REFERENCE OUTPUT LOAD - 1M REF IN Figure 24. Reference Output Voltage vs. Output Load AD872A 0.1 F DIGITAL OUTPUTS REF GND 1.0 F + REF OUT In 28-lead packages, the AD872A output data is presented in twos complement format. Table III indicates offset binary and twos complement output for various analog inputs. Table III. Output Data Format Analog Input Figure 22. Typical Reference Decoupling Connection Digital Output Offset Binary 1111 1111 1111 1111 1111 1111 1000 0000 0000 0000 0000 0000 0000 0000 0000 Twos Complement OTR 0111 1111 1111 0111 1111 1111 0000 0000 0000 1000 0000 0000 1000 0000 0000 1 0 0 0 1 VINA-VINB 0.999756 V 0.999268 V 0V -1 V -1.000244 V With this capacitor in place, the noise on the reference output is approximately 28 V rms at room temperature. Figure 23 shows the typical temperature drift performance of the reference, while Figure 24 illustrates the variation in reference voltage with load currents. The output stage is designed to provide at least 2 mA of output current, allowing a single reference to drive up to four AD872As, or other external loads. The power supply rejection of the reference is better than -54 dB at dc. Users requiring offset binary encoding may simply invert the MSB pin. In the 44-terminal surface mount packages, both MSB and MSB bits are provided. The AD872A features a digital out-of-range (OTR) bit that goes high when the input exceeds positive full scale or falls below negative full scale. As Table III indicates, the output bits will be set appropriately according to whether it is an out-of-range high -12- REV. A AD872A condition or an out-of-range low condition. Note that if the input is driven beyond +1.5 V, the digital outputs may not stay at +FS, but may actually fold back to midscale. The AD872A's CMOS digital output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause glitches on the supplies and may affect S/(N+D) performance. Applications requiring the AD872A to drive large capacitive loads or large fanout may require additional decoupling capacitors on DRVDD and DVDD. In extreme cases, external buffers or latches could be used. THREE-STATE OUTPUTS In this case, a 20 MHz clock is divided by 2 to produce the 10 MHz clock input for the AD872A. In this configuration, the duty cycle of the 20 MHz clock is irrelevant. The input circuitry for the CLKIN pin is designed to accommodate both TTL and CMOS inputs. The quality of the logic input, particularly the rising edge, is critical in realizing the best possible jitter performance for the part: the faster the rising edge, the better the jitter performance. As a result, careful selection of the logic family for the clock driver, as well as the fanout and capacitive load on the clock line, is important. Jitter-induced errors become more pronounced at higher frequency, large amplitude inputs, where the input slew rate is greatest. The AD872A is designed to support a sampling rate of 10 MSPS; running at slightly faster clock rates may be possible, although at reduced performance levels. Conversely, some slight performance improvements might be realized by clocking the AD872A at slower clock rates. Figure 27 presents the S/(N+D) vs. clock frequency for a 1 MHz analog input. 75 The 44-terminal surface mount AD872A offers three-state outputs. The digital outputs can be placed into a three-state mode by pulling the OUTPUT ENABLE (OEN) pin LOW. Note that this function is not intended to be used to pull the AD872A on and off a bus at 10 MHz. Rather, it is intended to allow the ADC to be pulled off the bus for evaluation or test modes. Also, to avoid corruption of the sampled analog signal during conversion (3 clock cycles), it is highly recommended that the AD872A be placed on the bus prior to the first sampling. OEN 70 tDD DATA OUTPUT ACTIVE tHL S/(N+D) - dB 65 THREE-STATE 60 Figure 25. Three-State Output Timing Diagram For timing budgetary purposes, the typical access and float delay times for the AD872A are 50 ns. CLOCK INPUT 55 50 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY - MHz The AD872A internal timing control uses the two edges of the clock input to generate a variety of internal timing signals. The optimal clock input should have a 50% duty cycle; however, sensitivity to duty cycle is significantly reduced for clock rates of less than 10 megasamples per second. +5V Figure 27. Typical S/(N+D) vs. Clock Frequency, fIN = 1 MHz, Full-Scale Input The power dissipated by the correction logic and output buffers is largely proportional to the clock frequency; running at reduced clock rates provides a slight reduction in power consumption. Figure 28 illustrates this tradeoff. 1.09 D R Q 1.08 74XX74 20MHz S Q CLK POWER - W 1.07 +5V 1.06 Figure 26. Divide-by-Two Clock Circuit 1.05 Due to the nature of on-chip compensation circuitry, the duty cycle should be maintained between 40% and 60% even for clock rates less than 10 MSPS. One way to realize a 50% duty cycle clock is to divide down a clock of higher frequency, as shown in Figure 26. 1.04 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY - MHz Figure 28. Typical Power Dissipation vs. Clock Frequency REV. A -13- AD872A ANALOG SUPPLIES AND GROUNDS DIGITAL SUPPLIES AND GROUNDS The AD872A features separate analog and digital supply and ground pins, helping to minimize digital corruption of sensitive analog signals. In general, AVSS and AVDD, the analog supplies, should be decoupled to AGND, the analog common, as close to the chip as physically possible. Care has been taken to minimize the signal dependence of the power supply currents; however, the analog supply currents will be proportional to the reference input. With REFIN at 2.5 V, the typical current into AVDD is 85 mA, while the typical current out of AVSS is 115 mA. Typically, 30 mA will flow into the AGND pin. Careful design and the use of differential circuitry provide the AD872A with excellent rejection of power supply noise over a wide range of frequencies, as illustrated in Figure 29. -75 SUPPLY REJECTION - dB -80 AVSS The digital activity on the AD872A chip falls into two general categories: CMOS correction logic, and CMOS output drivers. The internal correction logic draws relatively small surges of current, mainly during the clock transitions; in the 44-terminal package, these currents flow through pins DGND and DVDD. The output drivers draw large current impulses while the output bits are changing. The size and duration of these currents are a function of the load on the output bits: large capacitive loads are to be avoided. In the 44-terminal package, the output drivers are supplied through dedicated pins DRGND and DRVDD. Pin count constraints in the 28-lead packages require that the digital and driver supplies share package pins (although they have separate bond wires and on-chip routing). The decoupling shown in Figure 34 is appropriate for a reasonable capacitive load on the digital outputs (typically 20 pF on each pin). Applications involving greater digital loads should consider increasing the digital decoupling proportionately, and/or using external buffers/ latches. APPLICATIONS OPTIONAL ZERO AND GAIN TRIM -85 AVDD -90 DVDD -95 The AD872A is factory trimmed to minimize zero error, gain error and linearity errors. In some applications the zero and gain errors of the AD872A need to be externally adjusted to zero. If required, both zero error and gain error can be trimmed with external potentiometers as shown in Figure 31. Note that gain error adjustments must be made with an external reference. 107 -100 104 105 106 FREQUENCY - Hz Figure 29. Power Supply Rejection vs. Frequency, 100 mV p-p Signal on Power Supplies Zero trim should be adjusted first. Connect VINA to ground and adjust the 10 k potentiometer such that a nominal digital output code of 0000 0000 0000 (twos complement output) exists. Note that the zero trim should be decoupled and that the accuracy of the 2.5 V reference signals will directly affect the offset. Gain error may then be calibrated by adjusting the REF IN voltage. The REF IN voltage should be adjusted such that a +1 V input on VINA results in the digital output code 01111 1111 1111 (twos complement output). Figure 30 shows the degradation in SNR resulting from 100 mV of power supply ripple at various frequencies. As Figure 30 shows, careful decoupling is required to realize the specified dynamic performance. Figure 34 demonstrates the recommended decoupling strategy for the supply pins. Note that in extremely noisy environments, a more elaborate supply filtering scheme may be necessary. 70 +2.5V AD872A AD872A VOUT REF IN DVDD 10k 10 F 0.1 F V INB REF43 TRIM 100k 65 AVSS SNR - dB 60 AVDD -2.5V (a) ZERO TRIM (b) GAIN TRIM 55 Figure 31. Zero and Gain Error Trims DIGITAL OFFSET CORRECTION 50 104 105 106 FREQUENCY - Hz 107 Figure 30. SNR vs. Supply Noise Frequency (fIN = 1 MHz) The AD872A provides differential inputs that may be used to correct any offset voltages on the analog input. For applications where the input signal contains a dc offset, it may be advantageous to apply a nulling voltage to the VINB input. Applying a voltage equal to the dc offset will maximize the full-scale input range and therefore the dynamic range. Offsets ranging from -0.7 V to +0.5 V can be corrected. -14- REV. A AD872A Figure 32 shows how a dc offset can be applied using the AD568 12-bit, high speed digital-to-analog converter (DAC). This circuit can be used for applications requiring offset adjustments on every clock cycle. The AD568 connection scheme is used to provide a -0.512 V to +0.512 V output range. The offset voltage must be stable on the rising edge of the AD872A clock input. VIN 1 VINA In order to maximize the spurious free dynamic range of the circuit in Figure 33 it is advantageous to present a small signal to the input of the AD9100 and then amplify the output to the AD872A's full-scale input range. This can be accomplished with a low distortion, wide bandwidth amplifier such as the AD9617. The circuit uses a gain of 3.5 to optimize S/(N+D). For small scale input signals (-20 dB, -40 dB), the AD872A performs better without the track-and-hold because slewlimiting effects are no longer dominant. To gain the advantages of the added track-and-hold, it is important to give the AD872A a full-scale input. An alternative to the configuration presented above is to use the AD9101 track-and-hold amplifier. The AD9101 provides a built-in post amplifier with a gain of 4, providing excellent ac characteristics in conjunction with a high level of integration. As illustrated in Figure 33, it is necessary to skew the AD872A sample clock and the AD9100 sample/hold control. Clock skew (tS) is defined as the time starting at the AD9100's transition into hold mode and ending at the moment the AD872A samples. The AD872A samples on the rising edge of the sample clock, and the AD9100 samples on the falling edge of the sample/hold control. The choice of tS is primarily determined by the settling time of the AD9100. The droop rate of the AD9100 must also be taken into consideration. Using these values, the ideal tS is 17 ns. When choosing clock sources, it is extremely important that the front end track-and-hold sample/hold control is given a very low jitter clock source. This is not as crucial for the AD872A sample clock, because it is sampling a dc signal. +VS AD872A 8 DIGITAL OFFSET WORD 74 HC 574 74 HC 574 8 AD568 IBPO IOUT RL ACOM LCOM REF COM 2 VINB 4 4 Figure 32. Offset Correction Using the AD568 UNDERSAMPLING USING THE AD872A AND AD9100 The AD872A's on-chip THA optimizes transient response while maintaining low noise performance. For super-Nyquist (undersampling) applications it may be necessary to use an external THA with fast track-mode slew rate and hold mode settling time. An excellent choice for this application is the AD9100, an ultrahigh speed track-and-hold amplifier. +VS -V S VI N 10 F 4 RT 14 16 20 +5V 3.3 F 0.1 F CLOCK 2 IN AD9100 CLOCK 1 IN RT 9 10 510 510 1 5 7 AD 96685 4 8 7 Q 19 18 Q 2 3 8 10 17 13 +VS = 5.0V -VS = -5.2V -VS -VS 12 11 1 5 7 6 15 -5V 127 2 3 4 AD 9617 0.1 F 442 8* 5* 6 AIN AD872A EB 0.1 F 0.1 F 3.3 F * OPTIONAL, SEE AD9617 DATASHEET ALL CAPACITORS ARE 0.01 F (LOW INDUCTANCE - DECOUPLING) UNLESS OTHERWISE NOTED. 10 F -VS T = 200ns +5V CLOCK 2 0V t S = 17ns CLOCK 1 tS T = 200ns +1V -1V Figure 33. Undersampling Using the AD872A and AD9100 REV. A -15- AD872A +5A +5D R3 10 4 AVDD DVDD DGND 7 C13 0.1 C14 0.1 R2 49.9 CLOCK INPUT J2 TP2 JP3 P1 40-PIN IDC CONN. 1 C12 0.1 5 ANALOG IN J1 TP1 R1 49.9 C20 10pF 2 VINB 27 REF GND C7 10 F JP1 C18 0.1 28 REF IN JP2 26 REF OUT 8 7 6 C21 1F JP 1 VINA 6 JP4 JP8 R4 R5 20 +5D AGND DRVDD DGND 22 C15 0.1 C16 0.1 U3 74HC04 3 1 2 5 6 JP7 R6 20 4 JP9 R7 20 R8 20 JP10 R9 20 R10 20 R11 20 R12 20 R13 20 R14 20 R15 20 R16 20 23 JP6 21 20 19 18 17 16 15 14 13 12 11 10 9 8 24 JP5 AD872A CLK OTR MSB BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 BIT 10 BIT 11 BIT 12 AGND U2 REF43 +5A 1 2 VIN 3 4 * 11 AVSS 3 C11 0.1 -5A TP5 +5A AVSS 25 C17 0.1 VOUT 5 GND C22 0.1 *NOTE: JP11 SHOULD BE OPEN +5VA C2 0.01 AGND C1 0.01 -5VA FB1 C5 22 F C4 22 F FB2 TP6 C9 0.1 C8 0.1 TP4 R17 20 -5A TP3 +5D +5VD C3 0.01 DGND FB3 C6 22 F C10 0.1 TP7 40 Figure 34. AD872A/AD871 Evaluation Board Schematic -16- REV. A AD872A Figure 35. Silkscreen Layer PCB Layout (Not Shown to Scale) Table IV. Components List Reference Designator R1, R2 R3 R4-R17 C1-C3 C4-C6 C7 C8-C19, C22 C20 C21 U1 U2 U3 FB1-FB3 J1, J2 JP2, 3, 5, 7, 10 JP1-JP11 P1 Description Resistor, 1%, Metal Film, 49.9 Resistor, 1%, Metal Film, 10 Resistor, 1%, Metal Film, 20 SMD Chip Capacitor, 0.01 F Capacitor, Tantalum, 22 F Capacitor, Tantalum, 10 F SMD Chip Capacitor, 0.1 F Capacitor, Mica, 10 pF Capacitor, Ceramic, 1 F AD872A REF43B 74HC04N Ferrite Bead BNC Jack Jumpers Headers 40-Pin IDC Connector Quantity 2 1 14 3 3 1 13 1 1 1 1 1 3 2 5 11 1 REV. A -17- AD872A Figure 36. Component Side PCB Layout (Not Shown to Scale) Figure 37. Solder Side PCB Layout (Not Shown to Scale) -18- REV. A AD872A Figure 38. Ground Layer PCB Layout (Not Shown to Scale) Figure 39. Power Layer PCB Layout (Not Shown to Scale) REV. A -19- AD872A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Side Brazed DIP (D-28) 0.005 (0.13) MIN 0.100 (2.54) MAX 28 15 0.610 (15.49) 0.500 (12.70) PIN 1 1 14 1.490 (37.85) MAX 0.225 (5.72) MAX 0.200 (5.08) 0.125 (3.18) 0.026 (0.66) 0.014 (0.36) 0.110 (2.79) 0.090 (2.29) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN SEATING PLANE 0.620 (15.75) 0.590 (14.99) 0.018 (0.46) 0.008 (0.20) 44-Terminal LCC (E-44A) 0.100 (2.54) 0.064 (1.63) 0.055 (1.40) 0.045 (1.14) 0.075 (1.91) REF 0.020 (0.51) REF x 45 6 1 40 0.050 (1.27) BSC BOTTOM VIEW 0.028 (0.71) 0.022 (0.56) 28 18 0.662 (16.82) SQ 0.640 (16.27) 0.040 (1.02) REF x 45 3 PLACES -20- REV. A PRINTED IN U.S.A. C2001a-0-11/97 This datasheet has been download from: www..com Datasheets for electronics components. |
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